SOI is a device processing technique that places an insulating layer (e.g. a buried oxide layer) over a silicon substrate. Transistors are then fabricated in a layer of silicon located on top of the insulating layer. This technique may allow circuits to operate at higher speeds and to consume less power due to reduced junction capacitance. These operational improvements make device processing on SOI the preferred method for high-performance digital systems.
Depending on the silicon thickness and the doping level, an SOI device can be manufactured as a fully or partially depleted structure. A partially depleted structure (PD) is formed in a semiconductor layer that is thick enough to ensure that the channel will not be fully depleted when the device is turned off. Fully depleted (FD) structures require ultra-thin silicon layers, which are difficult to manufacture. Because partially deleted PD structures are easier to manufacture, many SOI devices are PD structures.
However, there are operational issues with the PD structures due to the “floating-body” effect, which is much less of an issue in the FD structures. The buried oxide layer creates a node, known as the body, which is not electrically connected to a fixed potential; and thus, is described as floating. The floating body effect causes several problems, such as the kink effect, drain current overshoot, single transistor latch, and reduced drain breakdown voltage.
At least two solutions have been proposed for overcoming the floating-body effect: biasing the substrate below the buried oxide layer or biasing the body directly. Of these two solutions, biasing of the body directly seems to be the most promising. The use of an H gate or a T gate layout method has been successfully used to bias the body directly, suppressing the floating-body effect. However, these methods increase the layout area required for the device, which is a big disadvantage for large-scale integration. In addition, these methods add unwanted parasitic gate oxide capacitance to the device, which degrades performance.
Min et al. propose using a modified shallow trench isolation (STI) method for reducing the parasitic capacitance in their article “Partial Trench Isolated Body-tied (PTIBT) Structure for SOI Applications,” which is fully incorporated by reference herein. However, the critical dimension and alignment associated with the additional lithography and etch steps required by this method are directly reflected in the transistor electrical width, which leads to larger design variation budgets that must be accounted for in the circuit design. This issue becomes much more critical as device specifications require smaller layouts. The cost of fabrication is significantly increased by the additional critical control of the processing steps required to minimize these effects.
Therefore, it would be desirable to bias the body of a PD SOI device structure in a manner that suppresses the floating-body effects inherent in a PD structure, while at the same time minimizing both the layout area of the device and the process complexity.